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this document provides an overview of the mcf5272 microprocessor features, including the major functional components. 1.1 features a block diagram of the mcf5272 is shown in figure 1. the main features are as follows: static version 2 coldfire variable-length risc processor ? 32-bit address and data path on-chip ? 66-mhz processor core and bus frequency ? sixteen general-purpose 32-bit data and address registers ? multiply-accumulate unit (mac) for dsp and fast multiply operations ? 63 dhrystone 2.1 mips at 66 mhz on-chip memories ? 4-kbyte sram on cpu internal bus ? 16-kbyte rom on cpu internal bus ? 1-kbyte instruction cache power management ? fully-static operation with processor sleep and whole-chip stop modes ? very rapid response to interrupts from the low-power sleep mode (wake-up feature) ? clock enable/disable for each peripheral when not used ? software-controlled disable of external clock input for virtually zero power consumption (low-power stop mode) two universal asynchronous/synchronous receiver transmitters (uarts) ? full-duplex operation ? based on mc68681 dual-uart (duart) programming model ? flexible baud rate generator ? modem control signals available (cts and r ts ) ? processor interrupt and wake-up capability ? enhanced tx, rx fifos, 24 bytes each a d v ance in f ormation mcf5272pb/d rev. 0, 1/2002 mcf5272 integrated microprocessor product brief f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2 mcf5272 integrated microprocessor product brief motorola features figure 1. mcf5272 block diagram jtag v2 coldfire processor complex 4-kbyte sram 1-kbyte sram controller rambar 4-entry store buffer 31 0 local memory local data bus instruction cache acr0 acr1 cacr local memory instruction unit cache controller 16-kbyte rom rom controller rombar instruction fetch fifo instruction buffer (3 x 32) decode, select, operand fetch address generation, execute ifp oep d[31:0] instruction address generation memory instruction bus sdram controller external bus interface system integration module (sim) 32-bit address bus 32-bit data bus interrupt controller cs [7:0] 88 8 4 icrs mbar piwr csors csbrs int [6:1] 6 dram controller outputs pivr pitr isr wrrr wirr alpr pmr system control base address dir identification sdram control sdcr parallel port four two uarts dma ethernet general- purpose timers control signals chip select module spr scr wcr wer usb qspi plic pacnt? pdcnt paddr? pcddr padr? pcdr sdram timer sdtr pwm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mcf5272 integrated microprocessor product brief 3 features ethernet module ? 10 baset capability, half- or full-duplex ? 100 baset capability, half duplex and limited throughput full-duplex (mcf5272) ? on-chip transmit and receive fifos ? off-chip exible buffer descriptor rings ? media-independent interface (mii) universal serial bus (usb) module ? 12 mbps (full-speed) ? fully compatible with usb 1.1 speci cations ? eight endpoints (control, bulk, interrupt rx, isochronous) ? endpoint fifos ? selectable on-chip analog interface external memory interface ? external glueless 8, 16, and 32-bit sram and rom interface bus ? sdram controller supports 16?256 mbit devices ? external bus con gurable for 16 or 32 bits width for sdram ? glueless interface to sram devices with or without byte strobe inputs ? programmable wait state generator queued serial peripheral interface (qspi) ? full-duplex, three-wire synchronous transfer ? up to four chip selects available ? master operation ? programmable master bit rates ? up to 16 preprogrammed transfers timer module ? 4x16-bit general-purpose multi-mode timer ? input capture and output compare pins for timers 1 and 2 ? programmable prescaler ? 15-ns resolution at 66-mhz clock frequency ? software watchdog timer ? software watchdog can generate interrupt before reset ? processor interrupt for each timer pulse width modulation (pwm) unit ? three identical channels ? independent prescaler tap point ? period/duty range variable system integration module (sim) ? system con guration including internal and external address mapping ? system protection by hardware watchdog f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4 mcf5272 integrated microprocessor product brief motorola mcf5272 architecture ? versatile programmable chip select signals with wait state generation logic ? up to three 16-bit parallel input/output ports ? latchable interrupt inputs with programmable priority and edge triggering ? programmable interrupt vectors for on-chip peripherals physical layer interface controller (plic) ? allows connection using general circuit interface (gci) or interchip digital link (idl) physical layer protocols for 2b + d data ? three physical interfaces ? four time-division multiplex (tdm) ports ieee 1149.1 boundary-scan test access port (jtag) for board-level testing operating voltage: 3.3 v 0.3 v operating temperature: 0 ?70 c operating frequency: dc to 66 mhz, from external cmos oscillator compact ultra low-pro le 196 ball-molded plastic ball-grid array package (pgba) 1.2 mcf5272 architecture this section brie y describes the mcf5272 core, sim, uart, and timer modules, and test access port. 1.2.1 version 2 coldfire core based on the concept of variable-length risc technology, coldfire combines the simplicity of conventional 32-bit risc architectures with a memory-saving, variable-length instruction set. the main features of the mcf5272 core are as follows: 32-bit address bus directly addresses up to 4 gbytes of address space 32-bit data bus variable-length risc optimized instruction set for high-level language constructs sixteen general-purpose 32-bit data and address registers mac unit for dsp applications supervisor/user modes for system protection vector base register to relocate exception-vector table special core interfacing signals for integrated memories full debug support the version 2 coldfire core has a 32-bit address bus and a 32-bit data bus. the address bus allows direct addressing of up to 4 gbytes. it supports misaligned data accesses and a bus arbitration unit for multiple bus masters. the version 2 coldfire supports an enhanced subset of the 68000 instruction set. the mac provides new instructions for dsp applications; otherwise, version 2 coldfire user code runs unchanged on 68020, 68030, 68040, and 68060 processors. the removed instructions include bcd, bit eld, logical rotate, f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mcf5272 integrated microprocessor product brief 5 mcf5272 architecture decrement and branch, integer division, and integer multiply with a 64-bit result. also, four indirect addressing modes have been eliminated. the coldfire 2 core incorporates a complete debug module that provides real-time trace, background debug mode, and real-time debug support. 1.2.2 system integration module (sim) the mcf5272 sim provides the external bus interface for the coldfire 2 architecture. it also eliminates most or all of the glue logic that typically supports the microprocessor and its interface with the peripheral and memory system. the sim provides programmable circuits to perform address-decoding and chip selects, wait-state insertion, interrupt handling, clock generation, discrete i/o, and power management features. 1.2.2.1 external bus interface the external bus interface (ebi) handles the transfer of information between the internal core and memory, peripherals, or other processing elements in the external address space. 1.2.2.2 chip select and wait state generation programmable chip select outputs provide signals to enable external memory and peripheral circuits, providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing. base memory address and block size are programmable, with some restrictions. for example, the starting address must be on a boundary that is a multiple of the block size. each chip select is general purpose; however, any one of the chip selects can be programmed to provide read and write enable signals suitable for use with most popular static rams and peripherals. data bus width (8-bit, 16-bit, or 32-bit) is programmable on all chip selects, and further decoding is available for protection from user mode access or read-only access. 1.2.2.3 system con guration and protection the sim provides con guration registers that allow general system functions to be controlled and monitored. for example, all on-chip registers can be relocated as a block by programming a module base address, power management modes can be selected, and the source of the most recent reset or berr can be checked. the hardware watchdog features can be enabled or disabled, and the bus time-out period can be programmed. a software watchdog timer is also provided for system protection. if programmed, the timer causes a reset to the mcf5272 if it is not refreshed periodically by software. 1.2.2.4 power management the sleep and stop power management modes reduce power consumption by allowing software to shut down the core, peripherals, or the whole device during inactive periods. to reduce power consumption further, software can individually disable internal clocks to the on-chip peripheral modules. the power-saving modes are described as follows: sleep mode uses interrupt control logic to allow any interrupt condition to wake the processor. as the mcf5272 is fully static, sleep mode is simply the disabling of the core?s clock after the current instruction completes. an interrupt from any internal or external source causes on-chip power f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6 mcf5272 integrated microprocessor product brief motorola mcf5272 architecture management logic to reenable the core?s clock; execution resumes with the next instruction. this allows rapid return from power-down state as compared to a dynamic implementation that must perform power-on reset processing before software can handle the interrupt request. if interrupts are enabled at the appropriate priority level, program control passes to the relevant interrupt service routine. stop mode is entered by the disabling of the external clock input and is achieved by software setting a bit in a control register. program execution stops after the current instruction. in stop mode, neither the core nor peripherals are active. the mcf5272 consumes very little power in this mode. to resume normal operation, the external interrupts cause the power management logic to re-enable the external clock input. the mcf5272 resumes program execution from where it entered stop mode (if no interrupt are pending), or starts interrupt exception processing if interrupts are pending. 1.2.2.5 parallel input/output ports the mcf5272 has up to three 16-bit general-purpose parallel ports, each line of which can be programmed as either an input or output. some port lines have dedicated pins and others are shared with other mcf5272 functions. some outputs have high drive current capability. 1.2.2.6 interrupt inputs the mcf5272 has exible latched interrupt inputs each of which can generate a separate, maskable interrupt with programmable interrupt priority level and triggering edge (falling or rising). each interrupt has its own interrupt vector. 1.2.3 uart module the mcf5272 has two full-duplex uart modules with an on-chip baud rate generator providing both standard and non-standard baud rates up to 5 mbps. the module is functionally equivalent to the mc68681 duart with enhanced features including 24-byte tx and rx fifos. data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity and up to 2 stop bits in 1/16-bit increments. receive and transmit fifos minimize cpu service calls. a wide variety of error detection and maskable interrupt capability is provided. using a programmable prescaler or an external source, the mcf5272 system clock supports various baud rates. modem support is provided with request-to-send (r ts ) and clear-to-send (cts ) lines available externally. full-duplex autoecho loopback, local loopback, and remote loopback modes can be selected. the uart can be programmed to interrupt or wake-up the cpu on various normal or abnormal events. to reduce power consumption, the uart can be disabled by software if not in use. 1.2.4 timer module the timer module contains ve timers arranged in two submodules. one submodule contains a programmable software watchdog timer. the other contains four independent, identical general-purpose timer units, each containing a free-running 16-bit timer for use in various modes, including capturing the timer value with an external event, counting external events, or triggering an external signal or interrupting the cpu when the timer reaches a set value. each unit has an 8-bit prescaler for deriving the clock input frequency from the system clock or external clock input. the output pin associated with each timer has programmable modes. to reduce power consumption, the timer module can be disabled by software. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mcf5272 integrated microprocessor product brief 7 system design 1.2.5 test access port for system diagnostics and manufacturing testing, the mcf5272 includes user-accessible test logic that complies with the ieee 1149.1 standard for boundary scan testing, often referred to as jtag (joint test action group). the ieee 1149.1 standard provides more information. 1.3 system design this section presents issues to consider when designing with the mcf5272. it describes differences between the mcf5272 (core and peripherals) and various other standard components that are replaced by moving to an integrated device like the mcf5272. 1.3.1 system bus con guration the mcf5272 has exibility in its system bus interfacing due to the dynamic bus sizing feature in which 32-,16-, and 8-bit data bus sizes are programmable on a per-chip select basis. the programmable nature of the strobe signals (including oe /rd , r/w , bs [3:0], and cs n ) should ensure that external decode logic is minimal or nonexistent. con guration software is required upon power-on reset before chip-selected devices can be used, except for chip select 0 (cs0 ), which is active after power-on reset until programmed otherwise. busw1 and busw0 select the initial data bus width for cs0 only. a wake-up from sleep mode or a restart from stop mode does not require recon guration of the chip select registers or other system con guration registers. 1.4 mcf5272-speci c features this section describes features peculiar to the mcf5272. 1.4.1 physical layer interface controller (plic) the physical layer interface controller (plic) allows the mcf5272 to connect at a physical level with external codecs and other peripheral devices that use either the general circuit interface (gci), or interchip digital link (idl), physical layer protocols. this module is primarily intended to facilitate designs that include isdn interfaces. 1.4.2 pulse-width modulation (pwm) unit the pwm unit is intended for use in control applications. with a suitable low-pass lter, it can be used as a digital-to-analog converter. this module generates a synchronous series of pulses. the duty cycle of the pulses is under software control. its main features include the following: double-buffered width register variable-divide prescale three identical, independent pwm modules byte-wide width register provides programmable control of duty cycle. the pwm implements a simple free-running counter with a width register and comparator such that the output is cleared when the counter exceeds the value of the width register. when the counter wraps around, f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8 mcf5272 integrated microprocessor product brief motorola mcf5272-speci c features its value is not greater than the width register value, and the output is set high. with a suitable low-pass lter, the pwm can be used as a digital-to-analog converter. 1.4.3 queued serial peripheral interface (qspi) the qspi module provides a serial peripheral interface with queued transfer capability. it supports up to 16 stacked transfers at a time, making cpu intervention between transfers unnecessary. transfer rams in the qspi are indirectly accessible using address and data registers. functionality is similar to the qspi portion of the qsm (queued serial module) implemented in the mc68332. the qspi has the following features: programmable queue to support up to 16 transfers without user intervention supports transfer sizes of 8 to 16 bits in 1-bit increments four peripheral chip-select lines for control of up to 15 devices baud rates from 129.4 kbps to 33 mbps at 66 mhz. programmable delays before and after transfers programmable clock phase and polarity supports wrap-around mode for continuous transfers 1.4.4 universal serial bus (usb) module the usb controller on the mcf5272 supports device mode data communications with a usb host (typically a pc). one host and up to 127 attached peripherals share usb bandwidth through a host-scheduled, token-based protocol. the usb uses a tiered star topology with a hub at the center of each star. each wire segment is a point-to-point connection between the host connector and a peripheral connector. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mcf5272 integrated microprocessor product brief 9 mcf5272-speci c features f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
10 mcf5272 integrated microprocessor product brief motorola mcf5272-speci c features f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mcf5272 integrated microprocessor product brief 11 mcf5272-speci c features f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcf5272pb/d how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre, 2 dai king street tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors document comments: fax (512) 933-2625 attn: tecd applications engineering information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and speci cally disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or speci cations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of cers, employees, subsidiaries, af liates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark of ce. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/af rmative action employer. ? motorola, inc. 2002 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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